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The Complete Verilog Book by Vivek Sagdeo (Hardcover, 1998)

The Verilog hardware description language provides the ability to describe digital and analogue systems for design concepts and implementation. It was developed originally at Gateway Design and implemented there. Now it is an open standard of IEEE and Open Verilog International and is supported by many tools and processes. This volume introduces the language and describes it in a comprehensive manner. In the book, each feature of the language is described using semantic introduction, syntax and examples. A chapter on semantics explains the basic concepts and algorithms that form the basis of every evaluation and every sequence of evaluations that ultimately provides the meaning or full semantics of the language. The book takes the approach that Verilog is not only a simulation language or a synthesis language or a formal method of describing design, but is a totality of all these and covers many aspects not covered before, but which are essential parts of any design process using Verilog. The text explains the data types in Verilog HDL, as the object-oriented world knows that the language-constructs and data types are equally important parts of a language. It explains the three views, behavioural, RTL and structural, and then describes features in each of these views. The volume aims to keep the reader abreast of developments in the Verilog world such as Verilog-A, cycle simulation, SD, and DCL, and uses IEEE 1364 syntax.

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