Best-selling in Non-Fiction Books
Save on Non-Fiction Books
- AU $9.86Trending at AU $16.84
- AU $11.51Trending at AU $18.82
- AU $24.83Trending at AU $25.31
- AU $64.07Trending at AU $74.95
- AU $28.70Trending at AU $37.00
- AU $44.73Trending at AU $47.15
- AU $24.97Trending at AU $28.26
About this product
- DescriptionThis research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed the location of the fault is kwn and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the JTAG port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. The measured data indicates there is consistently better replacement method regardless of the circuit congestion or location within the FPGA. Thus, given a specific location in the FPGA, there is preferred replacement method that will result in the lowest reconfiguration time.
- Author(s)Jason L Ives
- Date of Publication10/10/2012
- FormatPaperback / softback
- SubjectEducation & Teaching
- Country of PublicationUnited States
- Weight159 g
- Width189 mm
- Height246 mm
- Spine4 mm
- Format DetailsTrade paperback (US),Unsewn / adhesive bound
This item doesn't belong on this page.
Thanks, we'll look into this.