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About this product
- DescriptionThe Universal Verification Methodology is an industry standard used by many companies for verifying ASIC devices. In this book, you will find step-by-step instructions, coding guidelines and debugging features of UVM explained clearly using examples. The book also covers the changes from UVM-1.1d to UVM 1.2 and provides details of the enhancements in the upcoming IEEE 1800.2 UVM standard: http: //www.accellera.org/community/uvm/faq The Table of Contents, Preface, Foreword from UVM committee members and detailed information on this book is available on www.uvmbook.com.
- Author BiographySrivatsa Vasudevan is a Principal Engineer at Synopsys in Mountain View California USA. He works on cutting edge designs and has extensive verification experience. His expertise lies in Methodology, simulation performance and helping teams with complex technical challenges.
- Author(s)Srivatsa Vasudevan
- PublisherSrivatsa Vasudevan
- Date of Publication20/07/2016
- FormatPaperback / softback
- SubjectComputing: Professional & Programming
- Country of PublicationUnited States
- ImprintSrivatsa Vasudevan
- Content Noteblack & white illustrations
- Weight853 g
- Width203 mm
- Height254 mm
- Spine22 mm
- Format DetailsTrade paperback (US),Unsewn / adhesive bound
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