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- DescriptionThis book addresses front end questions and issues encountered in using the Verilog HDL, during all the stages of Hardware Design, Synthesis and Verification. The issues discussed in the book are typically encountered in both ASIC design projects as well as in Soft IP designs. These issues are addressed in a simple Q&A format. Since each issue is independently dealt with and explained in detail, this book acts as an important source of reference for the Verilog users. Each of the FAQs will be illustrated with figures and tables as required. The latest Verilog-2001 and SystemVerilog have also been referred to in this book. With the increasing complexity of ASICs being designed these days, the decisions that one makes in any of the stages of Design, Synthesis or Verification has profound effects on these three stages. This book presents the intricacies of these inter-dependent issues in the context of the Verilog HDL.
- Author(s)Needamangalam B. Balachander,Shivakumar S. Chonnad
- PublisherSpringer-Verlag New York Inc.
- Date of Publication01/12/2010
- SubjectElectronics Engineering & Communications Engineering
- Place of PublicationNew York, NY
- Country of PublicationUnited States
- ImprintSpringer-Verlag New York Inc.
- Content Noteblack & white illustrations
- Weight381 g
- Width156 mm
- Height234 mm
- Spine14 mm
- Format DetailsTrade paperback (US)
- Edition Statement1st ed. Softcover of orig. ed. 2004
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