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About this product
- DescriptionThe definition from SEMATECH of wafer level reliability test is: a methodology to assess the reliability impact of tools and processes by testing mechanism-specific test structures under accelerated conditions during device processing. Because wafer level reliability test is the accelerated test, it owns some different characters with common long time test in terms of failure mechanisms, test procedures, life time prediction, test structures design and so on. In this book, all items of wafer level reliability of CMOS devices and processes will be discussed. The purpose of this book is to provide a good and urgently need reference on MOS device reliability. The authors discuss how to enhance the veracity of lifetime prediction and the effects to degrade the veracity deeply. Finally, a discussion of the problems with wafer level reliability in terms of the engineering applications and research is given.
- PublisherNova Science Publishers Inc
- Date of Publication01/10/2008
- SubjectElectronics Engineering & Communications Engineering
- Place of PublicationNew York
- Country of PublicationUnited States
- ImprintNova Science Publishers Inc
- Content Notetables, charts & illus
- Weight608 g
- Width260 mm
- Height180 mm
- Edited byTerence B. Hook,Xinggong Wan,Yi Zhao
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