Electrical and Electronic Engineering Design Series Vol 3 CMOS Circcuit Design - Analog, digital, IC Layout This university level Electrical Engineering text is for anyone who wants to kw how to design products using CMOS circuits. The present text is unusually accessible to readers who want to acquire the skills of CMOS circuit design as well as the skill making Integrated Circuit Chip Layouts. We present a thorough foundation so that you can proceed to learn how to design and layout CMOS circuits. This text is different from other CMOS design texts, because t only do we actually show how to design CMOS circuits selecting transistor Length, Width and the correct value of mobility (a small detail that is usually overlooked if t igred) we show how to make accurate, functioning circuit layouts that can be used in a chip. Furthermore we ask you to work hard drawing over 60 layouts that give you real world experience. This is t about logic design. CMOS techlogy is the preferred techlogy for implementing modern digital and analog integrated circuits. We show, step by step, how layouts are made that conform to Mosis rules. A brief review of MOS transistors sets the stage for CMOS circuit design. Digital circuits with memory implement logic equations as sums of minterms (OR of ANDs) or products of maxterms (AND of ORs). We show how to design circuits such as NOT (Inverter), NAND, NOR, XOR, Multiplexer, and Adder. As we proceed we show how to plan and execute layouts for each circuit. One bit digital circuits with memory are used in state machines. The RS Latch is the most elementary one-bit circuit with memory. Latches do t have clock inputs, whereas flip-flops and edge triggered flip-flops are one-bit memory circuits with clock inputs. The flip-flops are synchrous circuits. We show how to design and layout the RS Latch and the D edge triggered flip-flop. We show that the JK design and layout is a straightforward adaptation of the D design and layout. The D and JK edge triggered flip-flops are the flip-flop circuits in commercial use today. Next the emphasis is on digital circuits that are an assembly of identical cells, such as the cell of a shift register. The integrated circuit layout of an assembly of cells is an orderly, repetitive pattern. Orderly, repetitive patterns are intrinsically free of layout errors. We say orderly layouts are mandatory for n trivial circuits (random logic layouts are high risk). We show how to make orderly systematic layouts, and how to write Spice programs that evaluate their performance. We design and layout well kwn digital circuits such as shift registers, storage registers with load control, registers on a bus, and programmable logic arrays of logic with memory. The well kwn current mirror, differential amplifier, operational amplifier, resistors and capacitors are designed and their performance is evaluated by Spice. Layout procedures for the circuits as well as the resistors and capacitors are presented. Spice is used to plot DC response, AC frequency response, and TRAN transient response performance of circuits that are analyzed and designed in the text. We show how to write these programs. We ask you to draw over 60 layouts, which we consider to be useful experiments that give you real world experience. We consider drawing the more than 60 layouts to be a significant learning activity. The presentations are eminently clear, because they are based on the policies assume thing and thing is obvious. The present text's contents are topics one actually uses when engaged in CMOS circuit analysis and design.