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- DescriptionThe UVM Primer uses simple, runnable code examples, accessible analogies, and an easy-to-read style to introduce you to the foundation of the Universal Verification Methodology. You will learn the basics of object-oriented programming with SystemVerilog and build upon that foundation to learn how to design testbenches using the UVM. Use the UVM Primer to brush up on your UVM kwledge before a job interview to be able to confidently answer questions such as What is a uvm_agent?, How do you use uvm_sequences?, and When do you use the UVM's factory. The UVM Primer's downloadable code examples give you hands-on experience with real UVM code. Ray Salemi uses online videos (on www.uvmprimer.com) to walk through the code from each chapter and build your confidence. Read The UVM Primer today and start down the path to the UVM.
- Author BiographyRay Salemi is a senior verification consultant with Mentor Graphics. Salemi started his career in Electronic Design Automation with Gateway Design Automation, the inventors of Verilog. Since then he has worked for Cadence Design Systems, Sun Microsystems, and several startups. Ray Salemi is the author of the popular introduction to simulation, FPGA SIMULATION.
- Author(s)Ray Salemi
- PublisherBoston Light Press
- Date of Publication23/10/2013
- FormatPaperback / softback
- SubjectComputing: Professional & Programming
- Country of PublicationUnited States
- ImprintBoston Light Press
- Content Noteblack & white illustrations
- Weight467 g
- Width216 mm
- Height280 mm
- Spine11 mm
- Format DetailsTrade paperback (US),Unsewn / adhesive bound
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