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Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler and PrimeTime by Himanshu Bhatnagar (Hardcover, 1999)

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Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-arounds described in detail.