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Hierarchical Modeling for VLSI Circuit Testing by Debashis Bhattacharya, John P. Hayes (Paperback, 2011)

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Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

Product Identifiers

Publisher
Springer-Verlag New York Inc.
ISBN-13
9781461288190
eBay Product ID (ePID)
189402014

Product Key Features

Subject Area
Electrical Engineering
Author
Debashis Bhattacharya, John P. Hayes
Publication Name
Hierarchical Modeling for Vlsi Circuit Testing
Format
Paperback
Language
English
Subject
Computer Science
Publication Year
2011
Type
Textbook
Number of Pages
160 Pages

Dimensions

Item Height
235mm
Item Width
155mm
Volume
89
Item Weight
278g

Additional Product Features

Title_Author
Debashis Bhattacharya, John P. Hayes
Series Title
The Springer International Series in Engineering and Computer Science
Country/Region of Manufacture
United States

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Hierarchical Modeling for VLSI Circuit Testing by Debashis Bhattacharya, John P. Hayes (Paperback, 2011)

About this product

Product Information

Product Identifiers

Product Key Features

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Additional Product Features

Best Selling in Adult Learning & University

Maps of Meaning: The Architecture of Belief by Jordan B. Peterson (1999, Paperback)

Eduqas GCSE (9-1) Religious Studies Route B: Catholic Christianity and Judaism by Deirdre Cleary, Andrew Barron, Joy White, Patrick Harrison (Paperback, 2017)

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Understanding and Treating Chronic Shame: Healing Right Brain Relational Trauma by Patricia A. DeYoung (Paperback, 2021)

Time Management by Peter Quarry (Paperback, 1986)

Save on Adult Learning & University

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